diff options
| author | Min-Yih Hsu <min.hsu@sifive.com> | 2025-03-27 11:00:07 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-03-27 11:00:07 -0700 |
| commit | aa207c3f054abb630be61cd60a11840a5c341c19 (patch) | |
| tree | 46b84eeb3d2816f22300545b7355aa447eab16cd /llvm/lib/Transforms/Utils/LoopUtils.cpp | |
| parent | 08aedf7201e296af532575685372bb5ff7ed8b01 (diff) | |
| download | llvm-aa207c3f054abb630be61cd60a11840a5c341c19.zip llvm-aa207c3f054abb630be61cd60a11840a5c341c19.tar.gz llvm-aa207c3f054abb630be61cd60a11840a5c341c19.tar.bz2 | |
[RISCV] Update the latency of floating point load in SiFive P500 scheduling model (#133165)
P500-series cores should have a floating point load latency closer to 5
cycles, just like P400- and P600-series cores.
Diffstat (limited to 'llvm/lib/Transforms/Utils/LoopUtils.cpp')
0 files changed, 0 insertions, 0 deletions