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| author | Craig Topper <craig.topper@sifive.com> | 2021-10-18 09:45:08 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2021-10-18 09:57:38 -0700 |
| commit | 84d9bc51a33bc4dfaab32473fe301170a984ca93 (patch) | |
| tree | 0cff1616f18e646862b8255c736b0e01652135a2 /llvm/lib/Transforms/Utils/LoopUtils.cpp | |
| parent | 239bdf461cae2c516849410c161066e556b1760e (diff) | |
| download | llvm-84d9bc51a33bc4dfaab32473fe301170a984ca93.zip llvm-84d9bc51a33bc4dfaab32473fe301170a984ca93.tar.gz llvm-84d9bc51a33bc4dfaab32473fe301170a984ca93.tar.bz2 | |
[RISCV] Rewrite forwardCopyWillClobberTuple to not assume that there are exactly 32 registers. NFC
This function was copied from ARM where register pairs/triples/quads can wrap around the 32 encoding space. So register 31 can pair with register 0. This is not true for RISCV vectors. The spec specifically mentions the possibility of a future encoding that has more than 32 registers.
This patch removes the modulo from the code and directly checks that destination register is in the source register range and not the beginning of the range. Though I don't expect an identity copy will occur.
Reviewed By: frasercrmck
Differential Revision: https://reviews.llvm.org/D111467
Diffstat (limited to 'llvm/lib/Transforms/Utils/LoopUtils.cpp')
0 files changed, 0 insertions, 0 deletions