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| author | Stephen Hines <srhines@google.com> | 2021-06-11 02:07:59 -0700 |
|---|---|---|
| committer | Stephen Hines <srhines@google.com> | 2021-06-11 02:13:48 -0700 |
| commit | 6455418d3d2a2de1a8251cc2ccf2e87b9ae3112d (patch) | |
| tree | 046a97171c96bc8076432a2e835e7adb0d76472c /llvm/lib/Transforms/Utils/LoopUtils.cpp | |
| parent | 47d138c93992f779a5dd0810b0e7402e043df61d (diff) | |
| download | llvm-6455418d3d2a2de1a8251cc2ccf2e87b9ae3112d.zip llvm-6455418d3d2a2de1a8251cc2ccf2e87b9ae3112d.tar.gz llvm-6455418d3d2a2de1a8251cc2ccf2e87b9ae3112d.tar.bz2 | |
[compiler-rt] [builtins] [AArch64] Add missing AArch64 data synchronization barrier (dsb) to __clear_cache
https://developer.arm.com/documentation/den0024/a/Caches/Cache-maintenance
covers how to properly clear caches on AArch64, and the builtin
implementation was missing a `dsb ish` after clearing the icache for the
selected range.
Reviewed By: kristof.beyls
Differential Revision: https://reviews.llvm.org/D104094
Diffstat (limited to 'llvm/lib/Transforms/Utils/LoopUtils.cpp')
0 files changed, 0 insertions, 0 deletions