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| author | Weining Lu <luweining@loongson.cn> | 2022-10-11 19:13:18 +0800 |
|---|---|---|
| committer | Weining Lu <luweining@loongson.cn> | 2022-10-11 19:51:48 +0800 |
| commit | 42b70793a1df473be9c78b4141d3f3cedcbac988 (patch) | |
| tree | b143d360b713c3c17c1d57a3be3d397bc96e0af1 /llvm/lib/Transforms/Utils/LoopUtils.cpp | |
| parent | 4e62d02db9309486e5f2c8433f2499b906ba114d (diff) | |
| download | llvm-42b70793a1df473be9c78b4141d3f3cedcbac988.zip llvm-42b70793a1df473be9c78b4141d3f3cedcbac988.tar.gz llvm-42b70793a1df473be9c78b4141d3f3cedcbac988.tar.bz2 | |
Reland "[Clang][LoongArch] Add inline asm support for constraints k/m/ZB/ZC"
Reference: https://gcc.gnu.org/onlinedocs/gccint/Machine-Constraints.html
k: A memory operand whose address is formed by a base register and
(optionally scaled) index register.
m: A memory operand whose address is formed by a base register and
offset that is suitable for use in instructions with the same
addressing mode as st.w and ld.w.
ZB: An address that is held in a general-purpose register. The offset
is zero.
ZC: A memory operand whose address is formed by a base register and
offset that is suitable for use in instructions with the same
addressing mode as ll.w and sc.w.
Note:
The INLINEASM SDNode flags in below tests are updated because the new
introduced enum `Constraint_k` is added before `Constraint_m`.
llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-inline-asm.ll
llvm/test/CodeGen/X86/callbr-asm-kill.mir
This patch passes `ninja check-all` on a X86 machine with all official
targets and the LoongArch target enabled.
Differential Revision: https://reviews.llvm.org/D134638
Diffstat (limited to 'llvm/lib/Transforms/Utils/LoopUtils.cpp')
0 files changed, 0 insertions, 0 deletions