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| author | Zhaoxuan Jiang <jiangzhaoxuan94@gmail.com> | 2023-11-23 16:21:27 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-11-23 08:21:27 +0000 |
| commit | 147c5d6686b935ecd93f8fa0e2dcf38deb593890 (patch) | |
| tree | 7638ec7ffb272ab6662ae832979dd7acbd69062d /llvm/lib/Transforms/Utils/LoopUtils.cpp | |
| parent | a3cab1fa17ebf29b01fcb566648e2f3fb2955993 (diff) | |
| download | llvm-147c5d6686b935ecd93f8fa0e2dcf38deb593890.zip llvm-147c5d6686b935ecd93f8fa0e2dcf38deb593890.tar.gz llvm-147c5d6686b935ecd93f8fa0e2dcf38deb593890.tar.bz2 | |
[AArch64] Allow LDR merge with same destination register by renaming (#71908)
The patch is based on a reverted patch:
https://reviews.llvm.org/D103597. It was trying to rename registers
before alias check, which is not safe and causes miscompiles. This patch
does 2 things:
1. Do the renaming with necessary checks passed, including alias check.
2. Rename the register for the instructions between the pairs and
combine the second load into the first. By doing so we can just check
the renamability between the pairs and avoid scanning unknown amount of
instructions before/after the pairs.
Necessary refactoring has been made in order to reuse as much code
possible with STR renaming.
Diffstat (limited to 'llvm/lib/Transforms/Utils/LoopUtils.cpp')
0 files changed, 0 insertions, 0 deletions