aboutsummaryrefslogtreecommitdiff
path: root/llvm/lib/Transforms/Utils/LoopUtils.cpp
diff options
context:
space:
mode:
authorSimon Tatham <simon.tatham@arm.com>2022-10-07 10:17:29 +0100
committerSimon Tatham <simon.tatham@arm.com>2022-10-11 13:27:20 +0100
commit0648e42e5281341ea3bdf075ff653a64f8356450 (patch)
treef161cc92b93d264a18b38f9ac5996460c9cc0cb2 /llvm/lib/Transforms/Utils/LoopUtils.cpp
parent2e9abc0c714a97b0412de8b09b74735fafa4432b (diff)
downloadllvm-0648e42e5281341ea3bdf075ff653a64f8356450.zip
llvm-0648e42e5281341ea3bdf075ff653a64f8356450.tar.gz
llvm-0648e42e5281341ea3bdf075ff653a64f8356450.tar.bz2
[NFC] Pre-commit tests for D135434.
pipeliner-preserve-ties.mir demonstrates a current bug in which the output of the Modulo Software Pipelining pass has left off a tie between operands in the conditional `t2ADDri` instruction. It should look like this: %19:rgpr = t2ADDri %1, 1, 1 /* CC::ne */, $cpsr, $noreg, implicit %1(tied-def 0) in which the final input operand is tied to the output, because that's the input that will become the output value if the conditionalized add instruction does not execute, and hence, must necessarily be whatever was in the output register beforehand. In the input to the pipeliner, those `tied-def` specifications are present and correct. But when the pipeliner clones MachineInstrs, it loses them. pipeliner-inlineasm.mir does not demonstrate any bug: the output is already correct, because of compensation code in the machine pipeliner that applies only to INLINEASM instructions. But no test previously exercised that code, so I add one now before making changes in that area.
Diffstat (limited to 'llvm/lib/Transforms/Utils/LoopUtils.cpp')
0 files changed, 0 insertions, 0 deletions