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authorLuo, Yuanke <yuanke.luo@intel.com>2022-05-03 18:57:25 +0800
committerLuo, Yuanke <yuanke.luo@intel.com>2022-05-24 13:18:42 +0800
commit496156ac57da3abd9c8a6dc422852b7bdfaa448f (patch)
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parent62a9b36fcf728b104ea87e6eb84c0be69b779df7 (diff)
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[X86][AMX] Multiple configure for AMX register.
The previous solution depends on variable name to record the shape information. However it is not reliable, because in release build compiler would not set the variable name. It can be accomplished with an additional option `fno-discard-value-names`, but it is not acceptable for users. This patch is to preconfigure the tile register with machine instruction. It follow the same way what sigle configure does. In the future we can fall back to multiple configure when single configure fails due to the shape dependency issue. The algorithm to configure the tile register is simple in the patch. We may improve it in the future. It configure tile register based on basic block. Compiler would spill the tile register if it live out the basic block. After the configure there should be no spill across tile confgiure in the register alloction. Just like fast register allocation the algorithm walk the instruction in reverse order. When the shape dependency doesn't meet, it insert ldtilecfg after the last instruction that define the shape. In post configuration compiler also walk the basic block to collect the physical tile register number and generate instruction to fill the stack slot for the correponding shape information. TODO: There is some following work in D125602. The risk is modifying the fast RA may cause regression as fast RA is usded for different targets. We may create an independent RA for tile register. Differential Revision: https://reviews.llvm.org/D125075
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