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| author | Craig Topper <craig.topper@sifive.com> | 2021-11-12 13:20:20 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2021-11-12 14:49:10 -0800 |
| commit | 02bed66cd5923a9964b7cb2211eae4bf3a065c6f (patch) | |
| tree | 3ee9046187aea511485c02a76786b9cce308c318 /llvm/lib/Transforms/Utils/LoopUnrollRuntime.cpp | |
| parent | 9a2b54af221717bf71040b530c4ac8043e1db23a (diff) | |
| download | llvm-02bed66cd5923a9964b7cb2211eae4bf3a065c6f.zip llvm-02bed66cd5923a9964b7cb2211eae4bf3a065c6f.tar.gz llvm-02bed66cd5923a9964b7cb2211eae4bf3a065c6f.tar.bz2 | |
[RISCV] Improve codegen for i32 udiv/urem by constant on RV64.
The division by constant optimization often produces constants that
are uimm32, but not simm32. These constants require 3 or 4 instructions
to materialize without Zba.
Since these instructions are often used by a multiply with a LHS
that needs to be zero extended with an AND, we can switch the MUL
to a MULHU by shifting both inputs left by 32. Once we shift the
constant left, the upper 32 bits no longer need to be 0 so constant
materialization is free to use LUI+ADDIW. This reduces the constant
materialization from 4 instructions to 3 in some cases while also
reducing the zero extend of the LHS from 2 shifts to 1.
Differential Revision: https://reviews.llvm.org/D113805
Diffstat (limited to 'llvm/lib/Transforms/Utils/LoopUnrollRuntime.cpp')
0 files changed, 0 insertions, 0 deletions