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| author | Jessica Paquette <jpaquette@apple.com> | 2020-02-11 10:22:38 -0800 |
|---|---|---|
| committer | Jessica Paquette <jpaquette@apple.com> | 2020-02-12 09:24:58 -0800 |
| commit | 45417b7aa7fcdd2aa75c1c809a3c7fb3292134be (patch) | |
| tree | 720bee25212dc40b7044fc3fc4081fbb5369c09d /llvm/lib/Transforms/Utils/LoopUnroll.cpp | |
| parent | 4f33a68973bfd9fa429b57528c3fe5443f59a734 (diff) | |
| download | llvm-45417b7aa7fcdd2aa75c1c809a3c7fb3292134be.zip llvm-45417b7aa7fcdd2aa75c1c809a3c7fb3292134be.tar.gz llvm-45417b7aa7fcdd2aa75c1c809a3c7fb3292134be.tar.bz2 | |
[AArch64][GlobalISel] Properly implement widening for TB(N)Z
When we have to widen to a 64-bit register, we have to emit a SUBREG_TO_REG.
Add a general-purpose widening helpe which emits the correct SUBREG_TO_REG
instruction based off of a desired size and add a testcase.
Also remove some asserts which are technically incorrect in `emitTestBit`.
- p0 doesn't count as a scalar type, so we need to check `!Ty.isVector()`
instead
- Whenever we have a s1, the Size/Bit checks are too conservative, so just
remove them
Replace these asserts with less conservative ones where applicable.
Differential Revision: https://reviews.llvm.org/D74427
Diffstat (limited to 'llvm/lib/Transforms/Utils/LoopUnroll.cpp')
0 files changed, 0 insertions, 0 deletions