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| author | Craig Topper <craig.topper@sifive.com> | 2022-12-01 11:09:38 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2022-12-01 11:09:38 -0800 |
| commit | e00e20a055fcd7386434f237784d845d5ddfc1b1 (patch) | |
| tree | 84b7e5ba0a56e439db80d0e17511410f1b5bec60 /llvm/lib/Transforms/Utils/InlineFunction.cpp | |
| parent | bf3f7016b17970478d1b8af481318c62d0a9004e (diff) | |
| download | llvm-e00e20a055fcd7386434f237784d845d5ddfc1b1.zip llvm-e00e20a055fcd7386434f237784d845d5ddfc1b1.tar.gz llvm-e00e20a055fcd7386434f237784d845d5ddfc1b1.tar.bz2 | |
[RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints.
These instructions requires both register operands to be compressible
so I've only applied the hint if we already have a GPRC physical register
assigned for the other register operand.
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D139079
Diffstat (limited to 'llvm/lib/Transforms/Utils/InlineFunction.cpp')
0 files changed, 0 insertions, 0 deletions