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| author | Hsiangkai Wang <kai.wang@sifive.com> | 2021-07-23 11:26:58 +0800 |
|---|---|---|
| committer | Hsiangkai Wang <kai.wang@sifive.com> | 2021-08-01 05:58:17 +0800 |
| commit | ee3aef93b73646ef98f0241498d807a4fb68b78c (patch) | |
| tree | 30d0630acf12624ccc4232de8379be21829c66e0 /llvm/lib/Transforms/Utils/GlobalStatus.cpp | |
| parent | 8b33839f010fe780fdaf68160be7c45d07fdfcad (diff) | |
| download | llvm-ee3aef93b73646ef98f0241498d807a4fb68b78c.zip llvm-ee3aef93b73646ef98f0241498d807a4fb68b78c.tar.gz llvm-ee3aef93b73646ef98f0241498d807a4fb68b78c.tar.bz2 | |
[RISCV][Docs] Add description about inline asm constraint for V.
Add inline asm constraint 'vr' for vector registers and 'vm' for vector
mask registers.
Differential Revision: https://reviews.llvm.org/D106633
Diffstat (limited to 'llvm/lib/Transforms/Utils/GlobalStatus.cpp')
0 files changed, 0 insertions, 0 deletions