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| author | Sander de Smalen <sander.desmalen@arm.com> | 2018-01-02 13:39:44 +0000 |
|---|---|---|
| committer | Sander de Smalen <sander.desmalen@arm.com> | 2018-01-02 13:39:44 +0000 |
| commit | c9b3e1cf039e541dac031bebac0fd075197d5860 (patch) | |
| tree | de7f6b9af6cd78dc347a74c590dad8c19f0d4642 /llvm/lib/Transforms/Utils/BasicBlockUtils.cpp | |
| parent | 016860cf2fa92698088a13d60259102546c7be29 (diff) | |
| download | llvm-c9b3e1cf039e541dac031bebac0fd075197d5860.zip llvm-c9b3e1cf039e541dac031bebac0fd075197d5860.tar.gz llvm-c9b3e1cf039e541dac031bebac0fd075197d5860.tar.bz2 | |
[AArch64][AsmParser] Add isScalarReg() and repurpose isReg()
Summary:
isReg() in AArch64AsmParser.cpp is a bit of a misnomer, and would be better named 'isScalarReg()' instead.
Patch [1/3] in a series to add operand constraint checks for SVE's predicated ADD/SUB.
Reviewers: rengolin, mcrosier, evandro, fhahn, echristo
Reviewed By: fhahn
Subscribers: aemerson, javed.absar, llvm-commits, kristof.beyls
Differential Revision: https://reviews.llvm.org/D41445
llvm-svn: 321646
Diffstat (limited to 'llvm/lib/Transforms/Utils/BasicBlockUtils.cpp')
0 files changed, 0 insertions, 0 deletions