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| author | sstwcw <su3e8a96kzlver@posteo.net> | 2023-12-02 19:26:07 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-12-02 19:26:07 +0000 |
| commit | b3e80d8ed251bfdad4a49fee19b8354eba407d1d (patch) | |
| tree | ccb9280edc6b3e6a89acadd785e40a3b7c10e8d5 /llvm/lib/Transforms/Utils/BasicBlockUtils.cpp | |
| parent | 5602636835e3fe655d196428091a64abd1837966 (diff) | |
| download | llvm-b3e80d8ed251bfdad4a49fee19b8354eba407d1d.zip llvm-b3e80d8ed251bfdad4a49fee19b8354eba407d1d.tar.gz llvm-b3e80d8ed251bfdad4a49fee19b8354eba407d1d.tar.bz2 | |
[clang-format] Add space in Verilog tagged unions (#71354)
In a tagged union expression, there should be a space between the field
name and the data. Previously, the tag could be recognized as part of a
dotted identifier or a struct literal, and the space would be omitted.
Diffstat (limited to 'llvm/lib/Transforms/Utils/BasicBlockUtils.cpp')
0 files changed, 0 insertions, 0 deletions