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| author | Tom Stellard <thomas.stellard@amd.com> | 2015-05-12 18:59:17 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2015-05-12 18:59:17 +0000 |
| commit | a77c3f7010cf7cd2fca38bf832b2d62bd2bcd918 (patch) | |
| tree | b5c587e874bdcdd2f5f57207088bbb40d3905337 /llvm/lib/Transforms/Utils/BasicBlockUtils.cpp | |
| parent | 9690fcf12eee2c91b106991b3aad7b0e65c0c1b3 (diff) | |
| download | llvm-a77c3f7010cf7cd2fca38bf832b2d62bd2bcd918.zip llvm-a77c3f7010cf7cd2fca38bf832b2d62bd2bcd918.tar.gz llvm-a77c3f7010cf7cd2fca38bf832b2d62bd2bcd918.tar.bz2 | |
R600/SI: Fix bug in VGPR spilling
AMDGPU::SI_SPILL_V96_RESTORE was missing from a switch statement, which
caused the srsrc and soffset register to not be set correctly.
This commit replaces the switch statement with a SITargetInfo query
to make sure all spill instructions are covered.
Differential Revision: http://reviews.llvm.org/D9582
llvm-svn: 237164
Diffstat (limited to 'llvm/lib/Transforms/Utils/BasicBlockUtils.cpp')
0 files changed, 0 insertions, 0 deletions