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| author | Craig Topper <craig.topper@sifive.com> | 2020-11-18 18:23:55 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2020-11-18 19:20:03 -0800 |
| commit | 6b0fc1f3c161295e6577d4c2237cefcb8e4dd9ba (patch) | |
| tree | 14c10dfcd53802f8bee9703090a3a455c7deba84 /llvm/lib/Transforms/Utils/BasicBlockUtils.cpp | |
| parent | bd106d74692fdc4d1eb79fb3a78da144f38791da (diff) | |
| download | llvm-6b0fc1f3c161295e6577d4c2237cefcb8e4dd9ba.zip llvm-6b0fc1f3c161295e6577d4c2237cefcb8e4dd9ba.tar.gz llvm-6b0fc1f3c161295e6577d4c2237cefcb8e4dd9ba.tar.bz2 | |
[RISCV] Add MemOperand to the instruction created by storeRegToStackSlot/loadRegFromStackSlot
Differential Revision: https://reviews.llvm.org/D91730
Diffstat (limited to 'llvm/lib/Transforms/Utils/BasicBlockUtils.cpp')
0 files changed, 0 insertions, 0 deletions