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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2020-01-21 22:46:43 -0500 |
|---|---|---|
| committer | Matt Arsenault <arsenm2@gmail.com> | 2020-01-23 12:04:20 -0500 |
| commit | 618fa77ae4dd8244e468fce0bf144fa329f41e5b (patch) | |
| tree | 9080ada2af199f2bf0d7029cb11a5aeca81ba1c4 /llvm/lib/Transforms/Utils/BasicBlockUtils.cpp | |
| parent | 4faf71a14338420afc09eec261d5295439ae956a (diff) | |
| download | llvm-618fa77ae4dd8244e468fce0bf144fa329f41e5b.zip llvm-618fa77ae4dd8244e468fce0bf144fa329f41e5b.tar.gz llvm-618fa77ae4dd8244e468fce0bf144fa329f41e5b.tar.bz2 | |
AMDGPU/GlobalISel: Select V_ADD3_U32/V_XOR3_B32
The other 3-op patterns should also be theoretically handled, but
currently there's a bug in the inferred pattern complexity.
I'm not sure what the error handling strategy should be for potential
constant bus violations. I think the correct strategy is to never
produce mixed SGPR and VGPR operands in a typical VOP instruction,
which will trivially avoid them. However, it's possible to still have
hand written MIR (or erroneously transformed code) with these
operands. When these fold, the restriction will be violated. We
currently don't have any verifiers for reg bank legality. For now,
just ignore the restriction.
It might be worth triggering a DAG fallback on verifier error.
Diffstat (limited to 'llvm/lib/Transforms/Utils/BasicBlockUtils.cpp')
0 files changed, 0 insertions, 0 deletions