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| author | David Green <david.green@arm.com> | 2021-03-17 15:29:02 +0000 |
|---|---|---|
| committer | David Green <david.green@arm.com> | 2021-03-17 15:29:02 +0000 |
| commit | 402f2cae7dcaba37ebe33e65bb4e2306ff752bfe (patch) | |
| tree | 550f8e76eed08bad81ff4001353f7a3890df2ab2 /llvm/lib/Transforms/Utils/BasicBlockUtils.cpp | |
| parent | f5963944d97d40300eeec8b43ae67aea2115398c (diff) | |
| download | llvm-402f2cae7dcaba37ebe33e65bb4e2306ff752bfe.zip llvm-402f2cae7dcaba37ebe33e65bb4e2306ff752bfe.tar.gz llvm-402f2cae7dcaba37ebe33e65bb4e2306ff752bfe.tar.bz2 | |
[ARM] Use lrdsb for more thumb1 loads.
Given a sextload i16, we can usually generate "ldrsh [rn. rm]". If we
don't naturally have a rn, rm addressing mode, we can either generate
"ldrh [rn, #0]; sxth" or "mov rm, #0; ldrsh [rn. rm]".
We currently generate the first, always creating a sxth. They are both
the same number of instructions, but if we generate the second then the
mov #0 will likely be CSE'd or pulled out of a loop, etc.
This adjusts the ISel patterns to do that, creating a mov instead of a
sxth.
Differential Revision: https://reviews.llvm.org/D98693
Diffstat (limited to 'llvm/lib/Transforms/Utils/BasicBlockUtils.cpp')
0 files changed, 0 insertions, 0 deletions