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| author | Craig Topper <craig.topper@sifive.com> | 2021-06-12 09:49:32 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2021-06-12 09:52:29 -0700 |
| commit | c997867dc084a1bcf631816f964b3ff49a297ba3 (patch) | |
| tree | 77d6270979b6a5edc7cd581c90bf0ae5598b71f0 /llvm/lib/Transforms/Instrumentation/ControlHeightReduction.cpp | |
| parent | 76f1baa7875acd88bdd4b431eed6e2d2decfc0fe (diff) | |
| download | llvm-c997867dc084a1bcf631816f964b3ff49a297ba3.zip llvm-c997867dc084a1bcf631816f964b3ff49a297ba3.tar.gz llvm-c997867dc084a1bcf631816f964b3ff49a297ba3.tar.bz2 | |
[X86] Add ISD::FREEZE and ISD::AssertAlign to the list of opcodes that don't guarantee upper 32 bits are zero.
The freeze issue was reported here
https://llvm.discourse.group/t/bug-or-feature-freeze-instruction/3639
I don't have a test for AssertAlign. I just noticed it was missing
and assume it should be similar to the other two Asserts.
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D104178
Diffstat (limited to 'llvm/lib/Transforms/Instrumentation/ControlHeightReduction.cpp')
0 files changed, 0 insertions, 0 deletions