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| author | Sylvestre Ledru <sylvestre@debian.org> | 2012-09-27 09:59:43 +0000 |
|---|---|---|
| committer | Sylvestre Ledru <sylvestre@debian.org> | 2012-09-27 09:59:43 +0000 |
| commit | 721cffd53a2c0e22167e042c53056b22e9363f67 (patch) | |
| tree | b6e17ac84f2d37247c1c76f5e7fa38cc422ea36a /llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp | |
| parent | a876013dc91bbd6bf4fe37c0d4cc7d1d5f5f4184 (diff) | |
| download | llvm-721cffd53a2c0e22167e042c53056b22e9363f67.zip llvm-721cffd53a2c0e22167e042c53056b22e9363f67.tar.gz llvm-721cffd53a2c0e22167e042c53056b22e9363f67.tar.bz2 | |
Fix a typo 'iff' => 'if'
llvm-svn: 164767
Diffstat (limited to 'llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp')
| -rw-r--r-- | llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp index 54be8ed..9857f6a 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp @@ -304,7 +304,7 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask, // If all of the demanded bits are known to be zero on one side or the // other, turn this into an *inclusive* or. - // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 + // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) if C1&C2 == 0 if ((DemandedMask & ~RHSKnownZero & ~LHSKnownZero) == 0) { Instruction *Or = BinaryOperator::CreateOr(I->getOperand(0), I->getOperand(1), @@ -315,7 +315,7 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask, // If all of the demanded bits on one side are known, and all of the set // bits on that side are also known to be set on the other side, turn this // into an AND, as we know the bits will be cleared. - // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 + // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 if (C1&C2) == C2 if ((DemandedMask & (RHSKnownZero|RHSKnownOne)) == DemandedMask) { // all known if ((RHSKnownOne & LHSKnownOne) == RHSKnownOne) { |