InstCombine: Don't unconditionally preserve 'nsw' when shrinking constants

Consider:
  %add = add nsw i32 %a, -16777216
  %and = and i32 %add, 255

Regardless of whether or not we demand the sign bit of %add, we cannot
replace -16777216 with 2130706432 without also removing 'nsw' from the
instruction.

This fixes PR20377.

llvm-svn: 216261

1 files changed, 8 insertions, 0 deletions

diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
index 1b42d3d..c26766a 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
@@ -43,6 +43,14 @@ static bool ShrinkDemandedConstant(Instruction *I, unsigned OpNo,
   // This instruction is producing bits that are not demanded. Shrink the RHS.
   Demanded &= OpC->getValue();
   I->setOperand(OpNo, ConstantInt::get(OpC->getType(), Demanded));
+
+  // If 'nsw' is set and the constant is negative, removing *any* bits from the
+  // constant could make overflow occur.  Remove 'nsw' from the instruction in
+  // this case.
+  if (auto *OBO = dyn_cast<OverflowingBinaryOperator>(I))
+    if (OBO->hasNoSignedWrap() && OpC->getValue().isNegative())
+      cast<BinaryOperator>(OBO)->setHasNoSignedWrap(false);
+
   return true;
 }