diff options
author | Craig Topper <craig.topper@intel.com> | 2017-07-16 05:37:58 +0000 |
---|---|---|
committer | Craig Topper <craig.topper@intel.com> | 2017-07-16 05:37:58 +0000 |
commit | 2072aca51cc8fd67c346e367fbeeab57722a46c5 (patch) | |
tree | d2cc84fed91bada83a40669fe0bb2612865b1230 /llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp | |
parent | 923ddad4c6ee78a7175b05e027eac8584b7facb6 (diff) | |
download | llvm-2072aca51cc8fd67c346e367fbeeab57722a46c5.zip llvm-2072aca51cc8fd67c346e367fbeeab57722a46c5.tar.gz llvm-2072aca51cc8fd67c346e367fbeeab57722a46c5.tar.bz2 |
[InstCombine] Move (0 - x) & 1 --> x & 1 to SimplifyDemandedUseBits.
This removes a dedicated matcher and allows us to support more than just an AND masking the lower bit.
llvm-svn: 308124
Diffstat (limited to 'llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp')
-rw-r--r-- | llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp index 5689c06..a20f474 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp @@ -417,8 +417,10 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask, // the highest demanded bit, we just return the other side. if (DemandedFromOps.isSubsetOf(RHSKnown.Zero)) return I->getOperand(0); - // We can't do this with the LHS for subtraction. - if (I->getOpcode() == Instruction::Add && + // We can't do this with the LHS for subtraction, unless we are only + // demanding the LSB. + if ((I->getOpcode() == Instruction::Add || + DemandedFromOps.isOneValue()) && DemandedFromOps.isSubsetOf(LHSKnown.Zero)) return I->getOperand(1); } |