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| author | Zain Jaffal <z_jaffal@apple.com> | 2022-12-08 08:21:53 +0200 |
|---|---|---|
| committer | Zain Jaffal <z_jaffal@apple.com> | 2022-12-12 14:45:54 +0000 |
| commit | ebae917294e680132fe1a3bc586a332dd47de8d0 (patch) | |
| tree | 66e205005c8116ddc2ca26db3b894e0c5b7fa9f1 /llvm/lib/Transforms/IPO/MergeFunctions.cpp | |
| parent | dfc8ab2e25dac2baddb36023991e6f88e12eb4bb (diff) | |
| download | llvm-ebae917294e680132fe1a3bc586a332dd47de8d0.zip llvm-ebae917294e680132fe1a3bc586a332dd47de8d0.tar.gz llvm-ebae917294e680132fe1a3bc586a332dd47de8d0.tar.bz2 | |
Recommit "[AArch64] Select SMULL for zero extended vectors when top bit is zero"
This is a recommit of f9e0390751cb5eefbbbc191f851c52422acacab1
The previous commit failed to handle cases where the zero extended operand is an extended `BUILD_VECTOR`.
We don't replace zext with a sext operand to select smull if any operand is `BUILD_VECTOR`
Original commit message:
we can safely replace a `zext` instruction with `sext` if the top bit is zero. This is useful because we can select `smull` when both operands are sign extended.
Reviewed By: fhahn, dmgreen
Differential Revision: https://reviews.llvm.org/D134711
Diffstat (limited to 'llvm/lib/Transforms/IPO/MergeFunctions.cpp')
0 files changed, 0 insertions, 0 deletions