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| author | Craig Topper <craig.topper@sifive.com> | 2021-05-10 12:12:16 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2021-05-11 09:29:31 -0700 |
| commit | dc00cbb5053895356955a6dc03632d4fa05048e3 (patch) | |
| tree | b99606a1d1856f140c6cca90bdd11d7f657e44d3 /llvm/lib/TextAPI/Platform.cpp | |
| parent | 668dccc396da4f593ac87c92dc0eb7bc983b5762 (diff) | |
| download | llvm-dc00cbb5053895356955a6dc03632d4fa05048e3.zip llvm-dc00cbb5053895356955a6dc03632d4fa05048e3.tar.gz llvm-dc00cbb5053895356955a6dc03632d4fa05048e3.tar.bz2 | |
[RISCV] Match trunc_vector_vl+sra_vl/srl_vl with splat shift amount to vnsra/vnsrl.
Limited to splats because we would need to truncate the shift
amount vector otherwise.
I tried to do this with new ISD nodes and a DAG combine to
avoid such a large pattern, but we don't form the splat until
LegalizeDAG and need DAG combine to remove a scalable->fixed->scalable
cast before it becomes visible to the shift node. By the time that
happens we've already visited the truncate node and won't revisit it.
I think I have an idea how to improve i64 on RV32 I'll save for a
follow up.
Reviewed By: frasercrmck
Differential Revision: https://reviews.llvm.org/D102019
Diffstat (limited to 'llvm/lib/TextAPI/Platform.cpp')
0 files changed, 0 insertions, 0 deletions