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author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2020-05-28 20:55:45 -0400 |
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committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2020-05-29 21:11:36 -0400 |
commit | 0892a96a05a8943457a4a3e2547923087aa06226 (patch) | |
tree | 7481aad7ce4c7c51b9f309d39a58fd5396c724b1 /llvm/lib/TextAPI/MachO/ArchitectureSet.cpp | |
parent | 4f300d499631504acdd32219254e939697202285 (diff) | |
download | llvm-0892a96a05a8943457a4a3e2547923087aa06226.zip llvm-0892a96a05a8943457a4a3e2547923087aa06226.tar.gz llvm-0892a96a05a8943457a4a3e2547923087aa06226.tar.bz2 |
AMDGPU: Optimize s_setreg_b32 to s_denorm_mode/s_round_mode
This is a custom inserter because it was less work than teaching
tablegen a way to indicate that it is sometimes OK to have a no side
effect instruction in the output of a side effecting pattern.
The asm is needed to look like a read of the mode register to prevent
it from being deleted. However, there seems to be a bug where the mode
register def instructions are moved across the asm sideeffect by the
post-RA scheduler.
Another oddity is the immediate is formatted differently between
s_denorm_mode and s_round_mode.
Diffstat (limited to 'llvm/lib/TextAPI/MachO/ArchitectureSet.cpp')
0 files changed, 0 insertions, 0 deletions