diff options
| author | Sudharsan Veeravalli <quic_svs@quicinc.com> | 2024-11-28 12:46:15 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-11-28 12:46:15 +0530 |
| commit | c4645ffedacad18e4cd1dd372288aa55178b1c44 (patch) | |
| tree | c498fc477687e92f8069fb208882dd22f56a8b3f /llvm/lib/TargetParser/RISCVISAInfo.cpp | |
| parent | 9ea5be639d31560faec993b4aebb3e10c7d4c8e2 (diff) | |
| download | llvm-c4645ffedacad18e4cd1dd372288aa55178b1c44.zip llvm-c4645ffedacad18e4cd1dd372288aa55178b1c44.tar.gz llvm-c4645ffedacad18e4cd1dd372288aa55178b1c44.tar.bz2 | |
[RISCV] Add Qualcomm uC Xqcicsr (CSR) extension (#117169)
The Qualcomm uC Xqcicsr extension adds 2 instructions that can read and
write CSRs.
The current spec can be found at:
https://github.com/quic/riscv-unified-db/releases/latest
This patch adds assembler only support.
Diffstat (limited to 'llvm/lib/TargetParser/RISCVISAInfo.cpp')
| -rw-r--r-- | llvm/lib/TargetParser/RISCVISAInfo.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp b/llvm/lib/TargetParser/RISCVISAInfo.cpp index c1bc441..cc5be59 100644 --- a/llvm/lib/TargetParser/RISCVISAInfo.cpp +++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp @@ -771,6 +771,10 @@ Error RISCVISAInfo::checkDependency() { return getIncompatibleError("xwchc", "zcb"); } + if (Exts.count("xqcicsr") != 0 && (XLen != 32)) { + return getError("'xqcicsr' is only supported for 'rv32'"); + } + return Error::success(); } |