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authorPreston Gurd <preston.gurd@intel.com>2013-01-04 20:54:54 +0000
committerPreston Gurd <preston.gurd@intel.com>2013-01-04 20:54:54 +0000
commite36b685a941e52371ff50c093444c444803f8ca8 (patch)
tree4859cb7cd1c3eb78f667e2a546cd28752d4eea9c /llvm/lib/Target/X86/X86TargetMachine.cpp
parent9ac69f9d37a5fe51afe6dc0c3b41e88199567ee5 (diff)
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The current Intel Atom microarchitecture has a feature whereby when a function
returns early then it is slightly faster to execute a sequence of NOP instructions to wait until the return address is ready, as opposed to simply stalling on the ret instruction until the return address is ready. When compiling for X86 Atom only, this patch will run a pass, called "X86PadShortFunction" which will add NOP instructions where less than four cycles elapse between function entry and return. It includes tests. Patch by Andy Zhang. llvm-svn: 171524
Diffstat (limited to 'llvm/lib/Target/X86/X86TargetMachine.cpp')
-rw-r--r--llvm/lib/Target/X86/X86TargetMachine.cpp4
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86TargetMachine.cpp b/llvm/lib/Target/X86/X86TargetMachine.cpp
index ea99796..8393f7e 100644
--- a/llvm/lib/Target/X86/X86TargetMachine.cpp
+++ b/llvm/lib/Target/X86/X86TargetMachine.cpp
@@ -190,6 +190,10 @@ bool X86PassConfig::addPreEmitPass() {
addPass(createX86IssueVZeroUpperPass());
ShouldPrint = true;
}
+ if (getX86Subtarget().padShortFunctions()){
+ addPass(createX86PadShortFunctions());
+ ShouldPrint = true;
+ }
return ShouldPrint;
}