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| author | Paul Walker <paul.walker@arm.com> | 2024-03-08 12:09:05 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-03-08 12:09:05 +0000 |
| commit | bd6eb54886ad12fb523e924e7291abfa2b010e3c (patch) | |
| tree | 854ea76359d2f50aa541a02d6c64e0afadeca478 /llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp | |
| parent | 4d478bcb4fc4fcf6532b725a0d070cb0c0cf9430 (diff) | |
| download | llvm-bd6eb54886ad12fb523e924e7291abfa2b010e3c.zip llvm-bd6eb54886ad12fb523e924e7291abfa2b010e3c.tar.gz llvm-bd6eb54886ad12fb523e924e7291abfa2b010e3c.tar.bz2 | |
[LLVM][CodeGen] Teach SelectionDAG how to expand FREM to a vector math call. (#83859)
This removes, at least when a vector library is available, a failure
case for scalable vectors. Doing so means we can confidently cost vector
FREM instructions without making an assumption that later passes will
transform the IR before it gets to the code generator.
NOTE: Whilst only FREM has been implemented the same mechanism
can be used for the other libm related ISD nodes.
Diffstat (limited to 'llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp')
0 files changed, 0 insertions, 0 deletions