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authorShengchen Kan <shengchen.kan@intel.com>2024-06-13 23:24:03 +0800
committerShengchen Kan <shengchen.kan@intel.com>2024-06-13 23:26:33 +0800
commit91a55cf5adbe37d33dc7b3b90de4bbb0b90761a1 (patch)
treeaf9bfa363a95125e5e5eabd358d92be1f66184e9 /llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
parent525c25acd364f018b4fa55e941bd702587478b1c (diff)
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[X86][MC] Not decode 0xf3 as rep prefix if it's right before REX2
This fixes https://github.com/llvm/llvm-project/issues/95412
Diffstat (limited to 'llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp')
-rw-r--r--llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp5
1 files changed, 4 insertions, 1 deletions
diff --git a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
index 0ff440b..6272e2d 100644
--- a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
+++ b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
@@ -284,7 +284,10 @@ static int readPrefixes(struct InternalInstruction *insn) {
// it's not mandatory prefix
// 3. if (nextByte >= 0x40 && nextByte <= 0x4f) it's REX and we need
// 0x0f exactly after it to be mandatory prefix
- if (isREX(insn, nextByte) || nextByte == 0x0f || nextByte == 0x66)
+ // 4. if (nextByte == 0xd5) it's REX2 and we need
+ // 0x0f exactly after it to be mandatory prefix
+ if (isREX(insn, nextByte) || isREX2(insn, nextByte) || nextByte == 0x0f ||
+ nextByte == 0x66)
// The last of 0xf2 /0xf3 is mandatory prefix
insn->mandatoryPrefix = byte;
insn->repeatPrefix = byte;