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author | Shengchen Kan <shengchen.kan@intel.com> | 2023-11-24 12:29:56 +0800 |
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committer | GitHub <noreply@github.com> | 2023-11-24 12:29:56 +0800 |
commit | 8c2537fde66406dd08021d28e302e1cdb862fc3f (patch) | |
tree | 14364168d20184b1f520b6dbd1d321b0a4cdbff8 /llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp | |
parent | be0307d5769f87a2e64b7e9e78a78bcd3dcca800 (diff) | |
download | llvm-8c2537fde66406dd08021d28e302e1cdb862fc3f.zip llvm-8c2537fde66406dd08021d28e302e1cdb862fc3f.tar.gz llvm-8c2537fde66406dd08021d28e302e1cdb862fc3f.tar.bz2 |
[X86][MC] Support encoding/decoding for PUSH2[P]/POP2[P] (#73233)
PUSH2 and POP2 are two new instructions for (respectively)
pushing/popping 2 GPRs at a time to/from
the stack. The opcodes of PUSH2 and POP2 are those of “PUSH r/m” and
“POP r/m” from legacy map 0, but we
require ModRM.Mod = 3 in order to disallow memory operand.
The 1-bit Push-Pop Acceleration hint described in #73092 applies to
PUSH2/POP2 too, then we have PUSH2P/POP2P.
For AT&T syntax, PUSH2[P] pushes the registers from right to left onto
the stack. POP2[P] pops the stack to registers from right to left. Intel
syntax has the opposite order - from left to right.
The assembly syntax is aligned with GCC & binutils
https://gcc.gnu.org/pipermail/gcc-patches/2023-November/637718.html
Diffstat (limited to 'llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp')
-rw-r--r-- | llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp index d5218d3..d50e651 100644 --- a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp +++ b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp @@ -150,6 +150,9 @@ static InstrUID decode(OpcodeType type, InstructionContext insnContext, dec = &THREEDNOW_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; break; + case MAP4: + dec = &MAP4_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; + break; case MAP5: dec = &MAP5_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; break; @@ -929,6 +932,9 @@ static bool readOpcode(struct InternalInstruction *insn) { case VEX_LOB_0F3A: insn->opcodeType = THREEBYTE_3A; return consume(insn, insn->opcode); + case VEX_LOB_MAP4: + insn->opcodeType = MAP4; + return consume(insn, insn->opcode); case VEX_LOB_MAP5: insn->opcodeType = MAP5; return consume(insn, insn->opcode); @@ -1100,6 +1106,9 @@ static int getInstructionIDWithAttrMask(uint16_t *instructionID, case THREEDNOW_MAP: decision = &THREEDNOW_MAP_SYM; break; + case MAP4: + decision = &MAP4_SYM; + break; case MAP5: decision = &MAP5_SYM; break; |