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| author | Tim Northover <tnorthover@apple.com> | 2014-04-28 11:27:43 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2014-04-28 11:27:43 +0000 |
| commit | 7b839f833d8c10f149da7fbfe97718505ffedf19 (patch) | |
| tree | 71017a8b7521a12e54cfe2add99ab41da3153baf /llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp | |
| parent | c00a7ff4b70c24b82069f5cb44477ccc8b9203cc (diff) | |
| download | llvm-7b839f833d8c10f149da7fbfe97718505ffedf19.zip llvm-7b839f833d8c10f149da7fbfe97718505ffedf19.tar.gz llvm-7b839f833d8c10f149da7fbfe97718505ffedf19.tar.bz2 | |
ARM64: diagnose use of v16-v31 in certain indexed NEON instructions.
Someone couldn't bear to have a completely orthogonal set of floating-point
registers, so we've got some instructions that only accept v0-v15 (coming in
ARMv9, V128_prime: you're allowed v2, v3, v5, v7, ...).
Anyway, we were permitting even the out of range registers during assembly
(CodeGen handled it correctly). This adds a diagnostic.
llvm-svn: 207412
Diffstat (limited to 'llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp')
0 files changed, 0 insertions, 0 deletions