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authorCraig Topper <craig.topper@sifive.com>2024-08-01 20:22:32 -0700
committerGitHub <noreply@github.com>2024-08-01 20:22:32 -0700
commit7a134f5ec55d611fb51b50f2a4f32b2b18b44ea1 (patch)
treedd37007b569ec7ff1b3241fab4873fabe7ad79ff /llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
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[RISCV] Use Zvhmin instead of Zvfh on RUN lines for some intrinsic tests. NFC (#101540)
Loads/stores/reinterpret/vfncvt.f.f.w/vfwcvt.f.f.v/vmerge/vmv.v.v are all expected to work for f16 vectors with Zvfhmin. Remove the handcrafted Zvfhmin test that partially tested this. Splits the vfwcvt.f.f.v and vfncvt.f.f.w tests into their own file so we can have a separate RUN line from the float<->int conversions.
Diffstat (limited to 'llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp')
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