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| author | Wang, Pengfei <pengfei.wang@intel.com> | 2021-08-10 11:18:40 +0800 |
|---|---|---|
| committer | Wang, Pengfei <pengfei.wang@intel.com> | 2021-08-10 12:46:01 +0800 |
| commit | 6f7f5b54c81be59ec7876649d1f9aa6b104658ec (patch) | |
| tree | b695ae7f4e450d1a6e818e40b5c51871e0c82753 /llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp | |
| parent | b978df4af4c8a668550fa035b70795312bf41f44 (diff) | |
| download | llvm-6f7f5b54c81be59ec7876649d1f9aa6b104658ec.zip llvm-6f7f5b54c81be59ec7876649d1f9aa6b104658ec.tar.gz llvm-6f7f5b54c81be59ec7876649d1f9aa6b104658ec.tar.bz2 | |
[X86] AVX512FP16 instructions enabling 1/6
1. Enable FP16 type support and basic declarations used by following patches.
2. Enable new instructions VMOVW and VMOVSH.
Ref.: https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html
Reviewed By: LuoYuanke
Differential Revision: https://reviews.llvm.org/D105263
Diffstat (limited to 'llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp | 32 |
1 files changed, 28 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp index 82581eb..44d83ef 100644 --- a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp +++ b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp @@ -150,6 +150,12 @@ static InstrUID decode(OpcodeType type, InstructionContext insnContext, dec = &THREEDNOW_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; break; + case MAP5: + dec = &MAP5_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; + break; + case MAP6: + dec = &MAP6_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode]; + break; } switch (dec->modrm_type) { @@ -332,7 +338,7 @@ static int readPrefixes(struct InternalInstruction *insn) { } if ((insn->mode == MODE_64BIT || (byte1 & 0xc0) == 0xc0) && - ((~byte1 & 0xc) == 0xc) && ((byte2 & 0x4) == 0x4)) { + ((~byte1 & 0x8) == 0x8) && ((byte2 & 0x4) == 0x4)) { insn->vectorExtensionType = TYPE_EVEX; } else { --insn->readerCursor; // unconsume byte1 @@ -876,11 +882,11 @@ static bool readOpcode(struct InternalInstruction *insn) { insn->opcodeType = ONEBYTE; if (insn->vectorExtensionType == TYPE_EVEX) { - switch (mmFromEVEX2of4(insn->vectorExtensionPrefix[1])) { + switch (mmmFromEVEX2of4(insn->vectorExtensionPrefix[1])) { default: LLVM_DEBUG( - dbgs() << format("Unhandled mm field for instruction (0x%hhx)", - mmFromEVEX2of4(insn->vectorExtensionPrefix[1]))); + dbgs() << format("Unhandled mmm field for instruction (0x%hhx)", + mmmFromEVEX2of4(insn->vectorExtensionPrefix[1]))); return true; case VEX_LOB_0F: insn->opcodeType = TWOBYTE; @@ -891,6 +897,12 @@ static bool readOpcode(struct InternalInstruction *insn) { case VEX_LOB_0F3A: insn->opcodeType = THREEBYTE_3A; return consume(insn, insn->opcode); + case VEX_LOB_MAP5: + insn->opcodeType = MAP5; + return consume(insn, insn->opcode); + case VEX_LOB_MAP6: + insn->opcodeType = MAP6; + return consume(insn, insn->opcode); } } else if (insn->vectorExtensionType == TYPE_VEX_3B) { switch (mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1])) { @@ -908,6 +920,12 @@ static bool readOpcode(struct InternalInstruction *insn) { case VEX_LOB_0F3A: insn->opcodeType = THREEBYTE_3A; return consume(insn, insn->opcode); + case VEX_LOB_MAP5: + insn->opcodeType = MAP5; + return consume(insn, insn->opcode); + case VEX_LOB_MAP6: + insn->opcodeType = MAP6; + return consume(insn, insn->opcode); } } else if (insn->vectorExtensionType == TYPE_VEX_2B) { insn->opcodeType = TWOBYTE; @@ -1043,6 +1061,12 @@ static int getInstructionIDWithAttrMask(uint16_t *instructionID, case THREEDNOW_MAP: decision = &THREEDNOW_MAP_SYM; break; + case MAP5: + decision = &MAP5_SYM; + break; + case MAP6: + decision = &MAP6_SYM; + break; } if (decision->opcodeDecisions[insnCtx] |