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| author | Sanjay Patel <spatel@rotateright.com> | 2023-01-08 11:36:21 -0500 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2023-01-08 12:04:09 -0500 |
| commit | 21d3871b7c90f85b3ae417724d7864369173bde0 (patch) | |
| tree | 2fa4ce5a9395c8bd7d0a082a8f67fd10df5e4179 /llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp | |
| parent | 310eea1c78e3e7aac7c016ab9bdf00d04f354645 (diff) | |
| download | llvm-21d3871b7c90f85b3ae417724d7864369173bde0.zip llvm-21d3871b7c90f85b3ae417724d7864369173bde0.tar.gz llvm-21d3871b7c90f85b3ae417724d7864369173bde0.tar.bz2 | |
[InstCombine] fold not-shift of signbit to icmp+zext, part 2
Follow-up to:
6c39a3aae1dc
That converted a pattern with ashr directly to icmp+zext, and
this updates the pattern that we used to convert to.
This canonicalizes to icmp for better analysis in the minimum case
and shortens patterns where the source type is not the same as dest type:
https://alive2.llvm.org/ce/z/tpXJ64
https://alive2.llvm.org/ce/z/dQ405O
This requires an adjustment to an icmp transform to avoid infinite looping.
Diffstat (limited to 'llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp')
0 files changed, 0 insertions, 0 deletions