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| author | Phoebe Wang <phoebe.wang@intel.com> | 2024-08-02 12:10:50 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-08-02 12:10:50 +0800 |
| commit | 10bad2c8d7be1bbb726c536dd306da3cae2247b4 (patch) | |
| tree | 4dcf574e2cda0a0a58205d11342b092878d2e6e1 /llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp | |
| parent | 96e6255e8b8b4e9e7bf0846df94dddcb79ced6f5 (diff) | |
| download | llvm-10bad2c8d7be1bbb726c536dd306da3cae2247b4.zip llvm-10bad2c8d7be1bbb726c536dd306da3cae2247b4.tar.gz llvm-10bad2c8d7be1bbb726c536dd306da3cae2247b4.tar.bz2 | |
[X86][AVX10.2] Support AVX10.2 option and VMPSADBW/VADDP[D,H,S] new instructions (#101452)
Ref.: https://cdrdv2.intel.com/v1/dl/getContent/828965
Diffstat (limited to 'llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp index 6272e2d..08922f4 100644 --- a/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp +++ b/llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp @@ -377,7 +377,7 @@ static int readPrefixes(struct InternalInstruction *insn) { // We simulate the REX2 prefix for simplicity's sake insn->rex2ExtensionPrefix[1] = (r2FromEVEX2of4(insn->vectorExtensionPrefix[1]) << 6) | - (x2FromEVEX3of4(insn->vectorExtensionPrefix[2]) << 5) | + (uFromEVEX3of4(insn->vectorExtensionPrefix[2]) << 5) | (b2FromEVEX2of4(insn->vectorExtensionPrefix[1]) << 4); } @@ -1217,15 +1217,19 @@ static int getInstructionID(struct InternalInstruction *insn, if (zFromEVEX4of4(insn->vectorExtensionPrefix[3])) attrMask |= ATTR_EVEXKZ; - if (bFromEVEX4of4(insn->vectorExtensionPrefix[3])) - attrMask |= ATTR_EVEXB; - if (isNF(insn) && !readModRM(insn) && + if (!readModRM(insn) && isNF(insn) && !isCCMPOrCTEST(insn)) // NF bit is the MSB of aaa. attrMask |= ATTR_EVEXNF; // aaa is not used a opmask in MAP4 else if (aaaFromEVEX4of4(insn->vectorExtensionPrefix[3]) && (insn->opcodeType != MAP4)) attrMask |= ATTR_EVEXK; + if (bFromEVEX4of4(insn->vectorExtensionPrefix[3])) { + attrMask |= ATTR_EVEXB; + if (uFromEVEX3of4(insn->vectorExtensionPrefix[2]) && + modFromModRM(insn->modRM) == 3) + attrMask |= ATTR_EVEXU; + } if (lFromEVEX4of4(insn->vectorExtensionPrefix[3])) attrMask |= ATTR_VEXL; if (l2FromEVEX4of4(insn->vectorExtensionPrefix[3])) |