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authorWouter van Oortmerssen <aardappel@gmail.com>2018-08-27 15:45:51 +0000
committerWouter van Oortmerssen <aardappel@gmail.com>2018-08-27 15:45:51 +0000
commit8a9cb242fb1a5fef9103a6df15d601ede83dba0b (patch)
treee5db7c6c38c6094df5363c442225dfe452007b62 /llvm/lib/Target/WebAssembly/WebAssemblyUtilities.cpp
parent5bda3fad0044008fe54b99a39141381cced2487c (diff)
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[WebAssembly] Added default stack-only instruction mode for MC.
Summary: Made it convert from register to stack based instructions, and removed the registers. Fixes to related code that was expecting register based instructions. Added the correct testing flag to all tests, depending on what the format they were expecting so far. Translated one test to stack format as example: reg-stackify-stack.ll tested: llvm-lit -v `find test -name WebAssembly` unittests/MC/* Reviewers: dschuff, sunfish Subscribers: sbc100, jgravelle-google, eraman, aheejin, llvm-commits, jfb Differential Revision: https://reviews.llvm.org/D51241 llvm-svn: 340750
Diffstat (limited to 'llvm/lib/Target/WebAssembly/WebAssemblyUtilities.cpp')
-rw-r--r--llvm/lib/Target/WebAssembly/WebAssemblyUtilities.cpp77
1 files changed, 75 insertions, 2 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyUtilities.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyUtilities.cpp
index f4884de..eed91e7 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyUtilities.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyUtilities.cpp
@@ -28,15 +28,25 @@ const char *const WebAssembly::PersonalityWrapperFn =
bool WebAssembly::isArgument(const MachineInstr &MI) {
switch (MI.getOpcode()) {
case WebAssembly::ARGUMENT_I32:
+ case WebAssembly::ARGUMENT_I32_S:
case WebAssembly::ARGUMENT_I64:
+ case WebAssembly::ARGUMENT_I64_S:
case WebAssembly::ARGUMENT_F32:
+ case WebAssembly::ARGUMENT_F32_S:
case WebAssembly::ARGUMENT_F64:
+ case WebAssembly::ARGUMENT_F64_S:
case WebAssembly::ARGUMENT_v16i8:
+ case WebAssembly::ARGUMENT_v16i8_S:
case WebAssembly::ARGUMENT_v8i16:
+ case WebAssembly::ARGUMENT_v8i16_S:
case WebAssembly::ARGUMENT_v4i32:
+ case WebAssembly::ARGUMENT_v4i32_S:
case WebAssembly::ARGUMENT_v2i64:
+ case WebAssembly::ARGUMENT_v2i64_S:
case WebAssembly::ARGUMENT_v4f32:
+ case WebAssembly::ARGUMENT_v4f32_S:
case WebAssembly::ARGUMENT_v2f64:
+ case WebAssembly::ARGUMENT_v2f64_S:
return true;
default:
return false;
@@ -46,9 +56,13 @@ bool WebAssembly::isArgument(const MachineInstr &MI) {
bool WebAssembly::isCopy(const MachineInstr &MI) {
switch (MI.getOpcode()) {
case WebAssembly::COPY_I32:
+ case WebAssembly::COPY_I32_S:
case WebAssembly::COPY_I64:
+ case WebAssembly::COPY_I64_S:
case WebAssembly::COPY_F32:
+ case WebAssembly::COPY_F32_S:
case WebAssembly::COPY_F64:
+ case WebAssembly::COPY_F64_S:
return true;
default:
return false;
@@ -58,9 +72,13 @@ bool WebAssembly::isCopy(const MachineInstr &MI) {
bool WebAssembly::isTee(const MachineInstr &MI) {
switch (MI.getOpcode()) {
case WebAssembly::TEE_I32:
+ case WebAssembly::TEE_I32_S:
case WebAssembly::TEE_I64:
+ case WebAssembly::TEE_I64_S:
case WebAssembly::TEE_F32:
+ case WebAssembly::TEE_F32_S:
case WebAssembly::TEE_F64:
+ case WebAssembly::TEE_F64_S:
return true;
default:
return false;
@@ -83,17 +101,29 @@ bool WebAssembly::isChild(const MachineInstr &MI,
bool WebAssembly::isCallDirect(const MachineInstr &MI) {
switch (MI.getOpcode()) {
case WebAssembly::CALL_VOID:
+ case WebAssembly::CALL_VOID_S:
case WebAssembly::CALL_I32:
+ case WebAssembly::CALL_I32_S:
case WebAssembly::CALL_I64:
+ case WebAssembly::CALL_I64_S:
case WebAssembly::CALL_F32:
+ case WebAssembly::CALL_F32_S:
case WebAssembly::CALL_F64:
+ case WebAssembly::CALL_F64_S:
case WebAssembly::CALL_v16i8:
+ case WebAssembly::CALL_v16i8_S:
case WebAssembly::CALL_v8i16:
+ case WebAssembly::CALL_v8i16_S:
case WebAssembly::CALL_v4i32:
+ case WebAssembly::CALL_v4i32_S:
case WebAssembly::CALL_v2i64:
+ case WebAssembly::CALL_v2i64_S:
case WebAssembly::CALL_v4f32:
+ case WebAssembly::CALL_v4f32_S:
case WebAssembly::CALL_v2f64:
+ case WebAssembly::CALL_v2f64_S:
case WebAssembly::CALL_EXCEPT_REF:
+ case WebAssembly::CALL_EXCEPT_REF_S:
return true;
default:
return false;
@@ -103,17 +133,29 @@ bool WebAssembly::isCallDirect(const MachineInstr &MI) {
bool WebAssembly::isCallIndirect(const MachineInstr &MI) {
switch (MI.getOpcode()) {
case WebAssembly::CALL_INDIRECT_VOID:
+ case WebAssembly::CALL_INDIRECT_VOID_S:
case WebAssembly::CALL_INDIRECT_I32:
+ case WebAssembly::CALL_INDIRECT_I32_S:
case WebAssembly::CALL_INDIRECT_I64:
+ case WebAssembly::CALL_INDIRECT_I64_S:
case WebAssembly::CALL_INDIRECT_F32:
+ case WebAssembly::CALL_INDIRECT_F32_S:
case WebAssembly::CALL_INDIRECT_F64:
+ case WebAssembly::CALL_INDIRECT_F64_S:
case WebAssembly::CALL_INDIRECT_v16i8:
+ case WebAssembly::CALL_INDIRECT_v16i8_S:
case WebAssembly::CALL_INDIRECT_v8i16:
+ case WebAssembly::CALL_INDIRECT_v8i16_S:
case WebAssembly::CALL_INDIRECT_v4i32:
+ case WebAssembly::CALL_INDIRECT_v4i32_S:
case WebAssembly::CALL_INDIRECT_v2i64:
+ case WebAssembly::CALL_INDIRECT_v2i64_S:
case WebAssembly::CALL_INDIRECT_v4f32:
+ case WebAssembly::CALL_INDIRECT_v4f32_S:
case WebAssembly::CALL_INDIRECT_v2f64:
+ case WebAssembly::CALL_INDIRECT_v2f64_S:
case WebAssembly::CALL_INDIRECT_EXCEPT_REF:
+ case WebAssembly::CALL_INDIRECT_EXCEPT_REF_S:
return true;
default:
return false;
@@ -123,18 +165,30 @@ bool WebAssembly::isCallIndirect(const MachineInstr &MI) {
unsigned WebAssembly::getCalleeOpNo(const MachineInstr &MI) {
switch (MI.getOpcode()) {
case WebAssembly::CALL_VOID:
+ case WebAssembly::CALL_VOID_S:
case WebAssembly::CALL_INDIRECT_VOID:
+ case WebAssembly::CALL_INDIRECT_VOID_S:
return 0;
case WebAssembly::CALL_I32:
+ case WebAssembly::CALL_I32_S:
case WebAssembly::CALL_I64:
+ case WebAssembly::CALL_I64_S:
case WebAssembly::CALL_F32:
+ case WebAssembly::CALL_F32_S:
case WebAssembly::CALL_F64:
+ case WebAssembly::CALL_F64_S:
case WebAssembly::CALL_EXCEPT_REF:
+ case WebAssembly::CALL_EXCEPT_REF_S:
case WebAssembly::CALL_INDIRECT_I32:
+ case WebAssembly::CALL_INDIRECT_I32_S:
case WebAssembly::CALL_INDIRECT_I64:
+ case WebAssembly::CALL_INDIRECT_I64_S:
case WebAssembly::CALL_INDIRECT_F32:
+ case WebAssembly::CALL_INDIRECT_F32_S:
case WebAssembly::CALL_INDIRECT_F64:
+ case WebAssembly::CALL_INDIRECT_F64_S:
case WebAssembly::CALL_INDIRECT_EXCEPT_REF:
+ case WebAssembly::CALL_INDIRECT_EXCEPT_REF_S:
return 1;
default:
llvm_unreachable("Not a call instruction");
@@ -144,11 +198,17 @@ unsigned WebAssembly::getCalleeOpNo(const MachineInstr &MI) {
bool WebAssembly::isMarker(const MachineInstr &MI) {
switch (MI.getOpcode()) {
case WebAssembly::BLOCK:
+ case WebAssembly::BLOCK_S:
case WebAssembly::END_BLOCK:
+ case WebAssembly::END_BLOCK_S:
case WebAssembly::LOOP:
+ case WebAssembly::LOOP_S:
case WebAssembly::END_LOOP:
+ case WebAssembly::END_LOOP_S:
case WebAssembly::TRY:
+ case WebAssembly::TRY_S:
case WebAssembly::END_TRY:
+ case WebAssembly::END_TRY_S:
return true;
default:
return false;
@@ -158,7 +218,9 @@ bool WebAssembly::isMarker(const MachineInstr &MI) {
bool WebAssembly::isThrow(const MachineInstr &MI) {
switch (MI.getOpcode()) {
case WebAssembly::THROW_I32:
+ case WebAssembly::THROW_I32_S:
case WebAssembly::THROW_I64:
+ case WebAssembly::THROW_I64_S:
return true;
default:
return false;
@@ -168,7 +230,9 @@ bool WebAssembly::isThrow(const MachineInstr &MI) {
bool WebAssembly::isRethrow(const MachineInstr &MI) {
switch (MI.getOpcode()) {
case WebAssembly::RETHROW:
+ case WebAssembly::RETHROW_S:
case WebAssembly::RETHROW_TO_CALLER:
+ case WebAssembly::RETHROW_TO_CALLER_S:
return true;
default:
return false;
@@ -178,8 +242,11 @@ bool WebAssembly::isRethrow(const MachineInstr &MI) {
bool WebAssembly::isCatch(const MachineInstr &MI) {
switch (MI.getOpcode()) {
case WebAssembly::CATCH_I32:
+ case WebAssembly::CATCH_I32_S:
case WebAssembly::CATCH_I64:
+ case WebAssembly::CATCH_I64_S:
case WebAssembly::CATCH_ALL:
+ case WebAssembly::CATCH_ALL_S:
return true;
default:
return false;
@@ -189,8 +256,11 @@ bool WebAssembly::isCatch(const MachineInstr &MI) {
bool WebAssembly::mayThrow(const MachineInstr &MI) {
switch (MI.getOpcode()) {
case WebAssembly::THROW_I32:
+ case WebAssembly::THROW_I32_S:
case WebAssembly::THROW_I64:
+ case WebAssembly::THROW_I64_S:
case WebAssembly::RETHROW:
+ case WebAssembly::RETHROW_S:
return true;
}
if (isCallIndirect(MI))
@@ -218,7 +288,9 @@ bool WebAssembly::isCatchTerminatePad(const MachineBasicBlock &MBB) {
bool SeenCatch = false;
for (auto &MI : MBB) {
if (MI.getOpcode() == WebAssembly::CATCH_I32 ||
- MI.getOpcode() == WebAssembly::CATCH_I64)
+ MI.getOpcode() == WebAssembly::CATCH_I64 ||
+ MI.getOpcode() == WebAssembly::CATCH_I32_S ||
+ MI.getOpcode() == WebAssembly::CATCH_I64_S)
SeenCatch = true;
if (SeenCatch && MI.isCall()) {
const MachineOperand &CalleeOp = MI.getOperand(getCalleeOpNo(MI));
@@ -235,7 +307,8 @@ bool WebAssembly::isCatchAllTerminatePad(const MachineBasicBlock &MBB) {
return false;
bool SeenCatchAll = false;
for (auto &MI : MBB) {
- if (MI.getOpcode() == WebAssembly::CATCH_ALL)
+ if (MI.getOpcode() == WebAssembly::CATCH_ALL ||
+ MI.getOpcode() == WebAssembly::CATCH_ALL_S)
SeenCatchAll = true;
if (SeenCatchAll && MI.isCall()) {
const MachineOperand &CalleeOp = MI.getOperand(getCalleeOpNo(MI));