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author | Dan Gohman <dan433584@gmail.com> | 2016-05-23 22:47:07 +0000 |
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committer | Dan Gohman <dan433584@gmail.com> | 2016-05-23 22:47:07 +0000 |
commit | 73d7a555b9fe75d0461dfdc52f5a085cb60d3127 (patch) | |
tree | 72f8a3c5f62b462ac3c58245403949e5b30fd323 /llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp | |
parent | 478c1a25fda3a1d007cfe2acdde1b259d358bc65 (diff) | |
download | llvm-73d7a555b9fe75d0461dfdc52f5a085cb60d3127.zip llvm-73d7a555b9fe75d0461dfdc52f5a085cb60d3127.tar.gz llvm-73d7a555b9fe75d0461dfdc52f5a085cb60d3127.tar.bz2 |
[WebAssembly] Basic TargetTransformInfo support for SIMD128.
llvm-svn: 270508
Diffstat (limited to 'llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp')
-rw-r--r-- | llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp index 3566317..bf546da 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.cpp @@ -25,3 +25,59 @@ WebAssemblyTTIImpl::getPopcntSupport(unsigned TyWidth) const { assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2"); return TargetTransformInfo::PSK_FastHardware; } + +unsigned WebAssemblyTTIImpl::getNumberOfRegisters(bool Vector) { + unsigned Result = BaseT::getNumberOfRegisters(Vector); + + // For SIMD, use at least 16 registers, as a rough guess. + if (Vector) + Result = std::max(Result, 16u); + + return Result; +} + +unsigned WebAssemblyTTIImpl::getRegisterBitWidth(bool Vector) { + if (Vector && getST()->hasSIMD128()) + return 128; + + return 64; +} + +unsigned WebAssemblyTTIImpl::getArithmeticInstrCost( + unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info, + TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo, + TTI::OperandValueProperties Opd2PropInfo) { + + unsigned Cost = BasicTTIImplBase<WebAssemblyTTIImpl>::getArithmeticInstrCost( + Opcode, Ty, Opd1Info, Opd2Info, Opd1PropInfo, Opd2PropInfo); + + if (VectorType *VTy = dyn_cast<VectorType>(Ty)) { + switch (Opcode) { + case Instruction::LShr: + case Instruction::AShr: + case Instruction::Shl: + // SIMD128's shifts currently only accept a scalar shift count. For each + // element, we'll need to extract, op, insert. The following is a rough + // approxmation. + if (Opd2Info != TTI::OK_UniformValue && + Opd2Info != TTI::OK_UniformConstantValue) + Cost = VTy->getNumElements() * + (TargetTransformInfo::TCC_Basic + + getArithmeticInstrCost(Opcode, VTy->getElementType()) + + TargetTransformInfo::TCC_Basic); + break; + } + } + return Cost; +} + +unsigned WebAssemblyTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, + unsigned Index) { + unsigned Cost = BasicTTIImplBase::getVectorInstrCost(Opcode, Val, Index); + + // SIMD128's insert/extract currently only take constant indices. + if (Index == -1u) + return Cost + 25 * TargetTransformInfo::TCC_Expensive; + + return Cost; +} |