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| author | Craig Topper <craig.topper@intel.com> | 2018-01-09 18:14:22 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-01-09 18:14:22 +0000 |
| commit | c4d2dd80b6d6bd446bfdbba0e084f1769aef59b6 (patch) | |
| tree | 74adcf75ee5f72431cbad3221b705f73ed726118 /llvm/lib/Target/WebAssembly/WebAssemblyTargetObjectFile.cpp | |
| parent | 243f20f1171e6730aa5b57ad28b10b50244dc2c9 (diff) | |
| download | llvm-c4d2dd80b6d6bd446bfdbba0e084f1769aef59b6.zip llvm-c4d2dd80b6d6bd446bfdbba0e084f1769aef59b6.tar.gz llvm-c4d2dd80b6d6bd446bfdbba0e084f1769aef59b6.tar.bz2 | |
[X86] Add a DAG combine to combine (sext (setcc)) with VLX
Normally target independent DAG combine would do this combine based on getSetCCResultType, but with VLX getSetCCResultType returns a vXi1 type preventing the DAG combining from kicking in.
But doing this combine can allow us to remove the explicit sign extend that would otherwise be emitted.
This patch adds a target specific DAG combine to combine the sext+setcc when the result type is the same size as the input to the setcc. I've restricted this to FP compares and things that can be represented with PCMPEQ and PCMPGT since we don't have full integer compare support on the older ISAs.
Differential Revision: https://reviews.llvm.org/D41850
llvm-svn: 322101
Diffstat (limited to 'llvm/lib/Target/WebAssembly/WebAssemblyTargetObjectFile.cpp')
0 files changed, 0 insertions, 0 deletions