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| author | Kees Cook <kees@kernel.org> | 2025-10-24 20:27:05 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-10-24 20:27:05 -0700 |
| commit | c9a45d3fd777997f669ff6af9c1f27e60a0fa23f (patch) | |
| tree | 0d7246e65b19659e3e3143497d6e0f6ced79c19d /llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp | |
| parent | 9161760123cd8b10694483a8f27d72ed134173b2 (diff) | |
| download | llvm-c9a45d3fd777997f669ff6af9c1f27e60a0fa23f.zip llvm-c9a45d3fd777997f669ff6af9c1f27e60a0fa23f.tar.gz llvm-c9a45d3fd777997f669ff6af9c1f27e60a0fa23f.tar.bz2 | |
[ARM][KCFI] Fix bundle sizes to reflect worst-case expansion (#164917)
The KCFI_CHECK pseudo-instruction size for ARM got miscalculated. These
should represent worst-case expansion to ensure correct branch range
calculations and code layout.
Update the Size field for each ARM sub-architecture:
- ARM: 28 → 40 bytes (10 instructions @ 4 bytes when r3 spill needed)
- Thumb2: 32 → 34 bytes (mixed 16/32-bit instructions with r3 spill)
- Thumb1: 50 → 38 bytes (19 instructions @ 2 bytes with r2+r3 spills)
The ARM and Thumb2 sizes were underestimating the case where the target
register is r12, requiring r3 to be used as scratch and
spilled/restored. The Thumb1 size was overestimated and has been
corrected to the actual worst-case of 19 instructions.
Diffstat (limited to 'llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp')
0 files changed, 0 insertions, 0 deletions