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authorMatt Arsenault <Matthew.Arsenault@amd.com>2022-02-17 16:52:02 -0500
committerMatt Arsenault <Matthew.Arsenault@amd.com>2022-02-17 18:30:56 -0500
commitc46aab01c002b7a04135b8b7f1f52d8c9ae23a58 (patch)
treee1ce64ee48a50588454225080d6c541d247ff06f /llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
parent822a1aad17288c23edd8a0c15f2c8130db66f262 (diff)
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RegAllocGreedy: Fix last chance recolor assert in impossible case
This example is not compilable without handling eviction of specific subregisters. Last chance recoloring was deciding it could try evicting an overlapping superregister, which doesn't help make any progress. The LiveIntervalUnion would then assert due to an overlapping / identical range when trying the new assignment. Unfortunately this is also producing a verifier error after the allocation fails. I've seen a number of these, and not sure if we should just start deleting the function on error rather than trying to figure out how to put together valid MIR. I'm not super confident this is the right place to fix this. I also have a number of failing testcases I need to fix by handling partial evictions of superregisters.
Diffstat (limited to 'llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp')
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