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| author | Craig Topper <craig.topper@intel.com> | 2017-12-22 17:18:13 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-12-22 17:18:13 +0000 |
| commit | b2368fbdf4e153e1b920cddd6f393434b3245f84 (patch) | |
| tree | 3d44b330bde3b39ebda85d3c5a65671079313834 /llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp | |
| parent | 576335f998dc1633db77d72f2957f2b7c2c84640 (diff) | |
| download | llvm-b2368fbdf4e153e1b920cddd6f393434b3245f84.zip llvm-b2368fbdf4e153e1b920cddd6f393434b3245f84.tar.gz llvm-b2368fbdf4e153e1b920cddd6f393434b3245f84.tar.bz2 | |
[SelectionDAG] Reverse the order of operands in the ISD::ADD created by TargetLowering::getVectorElementPointer so that the FrameIndex is on the left.
This seems to improve X86's ability to match this into an address computation. Otherwise the other operand gets assigned to the base register and the stack pointer + frame index ends up in the index register. But index registers can't encode ESP/RSP so we end up having to move it into another register to meet the constraint.
I could try to improve the address matcher in X86, but swapping the producer seemed easier. Several other places already have the operands in this order so this is at least consistent.
llvm-svn: 321370
Diffstat (limited to 'llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp')
0 files changed, 0 insertions, 0 deletions