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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-01-08 01:13:20 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-01-08 01:13:20 +0000 |
| commit | ae6f1e07fcc356f0c4a8615d74814c6f8aadbd72 (patch) | |
| tree | d92a1fd9b4d73148dc21bbf59a6ce249c21466d9 /llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp | |
| parent | 68c668a5f303dc6f2d05f108dee152e8d9f6cbfe (diff) | |
| download | llvm-ae6f1e07fcc356f0c4a8615d74814c6f8aadbd72.zip llvm-ae6f1e07fcc356f0c4a8615d74814c6f8aadbd72.tar.gz llvm-ae6f1e07fcc356f0c4a8615d74814c6f8aadbd72.tar.bz2 | |
AMDGPU/GlobalISel: Disallow VGPR->SCC copies
This fixes using scalar adds when only the carry in is a VGPR
using greedy regbankselect.
llvm-svn: 350593
Diffstat (limited to 'llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp')
0 files changed, 0 insertions, 0 deletions