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| author | Craig Topper <craig.topper@sifive.com> | 2022-12-21 12:08:07 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2022-12-21 12:26:01 -0800 |
| commit | 9fdf21f3d07d5efafec4334b1b4d200bc7811c05 (patch) | |
| tree | 1114250ce1c72643e5c9c1d96ffe1c6d176427d8 /llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp | |
| parent | dbc92f598ed0ea92a8f0eb4000d3120cc85ad3f5 (diff) | |
| download | llvm-9fdf21f3d07d5efafec4334b1b4d200bc7811c05.zip llvm-9fdf21f3d07d5efafec4334b1b4d200bc7811c05.tar.gz llvm-9fdf21f3d07d5efafec4334b1b4d200bc7811c05.tar.bz2 | |
[RISCV] Add test cases for i8/i16 abs followed by zext.
The andi, zext.h and slli+srli shift pairs at the end of the generated
output are unnecessary if the input is sign extended.
Diffstat (limited to 'llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp')
0 files changed, 0 insertions, 0 deletions