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authorJun Bum Lim <junbuml@codeaurora.org>2018-04-03 18:17:34 +0000
committerJun Bum Lim <junbuml@codeaurora.org>2018-04-03 18:17:34 +0000
commit7ab1b32b5e51168fe4823378399c9b559a383f86 (patch)
tree533696cf19f82052eb09ffb49672f6851a7ee552 /llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
parent2c5f94401565807a77f914875adeb9db7473ee73 (diff)
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[CodeGen]Add NoVRegs property on PostRASink and ShrinkWrap
Summary: This change declare that PostRAMachineSinking and ShrinkWrap require NoVRegs property, so now the MachineFunctionPass can enforce this check. These passes are disabled in NVPTX & WebAssembly. Reviewers: dschuff, jlebar, tra, jgravelle-google, MatzeB, sebpop, thegameg, mcrosier Reviewed By: dschuff, thegameg Subscribers: jholewinski, jfb, sbc100, aheejin, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D45183 llvm-svn: 329095
Diffstat (limited to 'llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp')
-rw-r--r--llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp5
1 files changed, 2 insertions, 3 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
index ec6843ee5..8151f25 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
@@ -264,16 +264,15 @@ void WebAssemblyPassConfig::addPostRegAlloc() {
// virtual registers. Consider removing their restrictions and re-enabling
// them.
- // Has no asserts of its own, but was not written to handle virtual regs.
- disablePass(&ShrinkWrapID);
-
// These functions all require the NoVRegs property.
disablePass(&MachineCopyPropagationID);
+ disablePass(&PostRAMachineSinkingID);
disablePass(&PostRASchedulerID);
disablePass(&FuncletLayoutID);
disablePass(&StackMapLivenessID);
disablePass(&LiveDebugValuesID);
disablePass(&PatchableFunctionID);
+ disablePass(&ShrinkWrapID);
TargetPassConfig::addPostRegAlloc();
}