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authorAlexandros Lamprineas <alexandros.lamprineas@arm.com>2015-11-29 10:43:59 +0000
committerAlexandros Lamprineas <alexandros.lamprineas@arm.com>2015-11-29 10:43:59 +0000
commit502592c1d4b4ed0ae203daaad63e6cb8e668d6d1 (patch)
tree1f9a6e9ea6f1cd76058283723f2f56804e0df638 /llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
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ARM v8.1a adds Advanced SIMD instructions for Rounding Double Multiply
Add/Subtract. The following instructions are added to AArch32 instruction set: - VQRDMLAH: Vector Saturating Rounding Doubling Multiply Accumulate Returning High Half - VQRDMLSH: Vector Saturating Rounding Doubling Multiply Subtract Returning High Half The following instructions are added to AArch64 instruction set: - SQRDMLAH: Signed Saturating Rounding Doubling Multiply Accumulate Returning High Half - SQRDMLSH: Signed Saturating Rounding Doubling Multiply Subtract Returning High Half This patch adds intrinsic and ACLE macro support for these instructions, as well as corresponding tests. Differential Revision: http://reviews.llvm.org/D14982 llvm-svn: 254250
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