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| author | Roman Lebedev <lebedev.ri@gmail.com> | 2021-08-02 16:42:00 +0300 |
|---|---|---|
| committer | Roman Lebedev <lebedev.ri@gmail.com> | 2021-08-02 20:21:37 +0300 |
| commit | 1e801439be26569c9ede6fd309a645b00adb656c (patch) | |
| tree | c0debce0977eba9bc4fccad96c88e54880576543 /llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp | |
| parent | f6c44cdd3773a74fe52127b78c494d07f909e74d (diff) | |
| download | llvm-1e801439be26569c9ede6fd309a645b00adb656c.zip llvm-1e801439be26569c9ede6fd309a645b00adb656c.tar.gz llvm-1e801439be26569c9ede6fd309a645b00adb656c.tar.bz2 | |
[InstCombine] `xor` reduction w/ i1 elt type is a parity check
For i1 element type, `xor` and `add` are interchangeable
(https://alive2.llvm.org/ce/z/e77hhQ), so we should treat it just like
an `add` reduction and consistently transform them both:
https://alive2.llvm.org/ce/z/MjCm5W (self)
https://alive2.llvm.org/ce/z/kgqF4M (skipped zext)
https://alive2.llvm.org/ce/z/pgy3HP (skipped sext)
Though, let's emit the IR that is similar to the one we produce for
`vector_reduce_add(<n x i1>)`.
See https://bugs.llvm.org/show_bug.cgi?id=51259
Diffstat (limited to 'llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp')
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