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| author | Nicolas Vasilache <nicolasvasilache@users.noreply.github.com> | 2023-06-21 14:35:30 +0000 |
|---|---|---|
| committer | Nicolas Vasilache <nicolasvasilache@users.noreply.github.com> | 2023-06-26 16:46:42 +0000 |
| commit | 1660f2174d59bc2fd04131dab9ab0b43178bf665 (patch) | |
| tree | 34906b1a6c562655423ddb88a3730943befe2a4a /llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp | |
| parent | b3272f5ddbfd2b4a3219df223392af7a09571cc1 (diff) | |
| download | llvm-1660f2174d59bc2fd04131dab9ab0b43178bf665.zip llvm-1660f2174d59bc2fd04131dab9ab0b43178bf665.tar.gz llvm-1660f2174d59bc2fd04131dab9ab0b43178bf665.tar.bz2 | |
[mlir][Transform] Add support for mma.sync m16n8k16 f16 rewrite.
This PR adds support for the m16n8k16 f16 case.
At this point, the support is mostly mechanical and could be Tablegen'd to all cases.
Until then, this can be populated as needed on a case-by-case basis.
Depends on: D153420
Differential Revision: https://reviews.llvm.org/D153428
Diffstat (limited to 'llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp')
0 files changed, 0 insertions, 0 deletions