aboutsummaryrefslogtreecommitdiff
path: root/llvm/lib/Target/WebAssembly/WebAssemblySubtarget.cpp
diff options
context:
space:
mode:
authorJF Bastien <jfb@google.com>2015-07-01 23:41:25 +0000
committerJF Bastien <jfb@google.com>2015-07-01 23:41:25 +0000
commit03855df197944840745afd1180ebf423c7050c3c (patch)
tree10279e6f356ea28fbb0e58df4b3eb958e1471b7a /llvm/lib/Target/WebAssembly/WebAssemblySubtarget.cpp
parent14cd13c51313e3a53a403eeb32b091d9c6a3011c (diff)
downloadllvm-03855df197944840745afd1180ebf423c7050c3c.zip
llvm-03855df197944840745afd1180ebf423c7050c3c.tar.gz
llvm-03855df197944840745afd1180ebf423c7050c3c.tar.bz2
WebAssembly: start instructions
Summary: * Add 64-bit address space feature. * Rename SIMD feature to SIMD128. * Handle single-thread model with an IR pass (same way ARM does). * Rename generic processor to MVP, to follow design's lead. * Add bleeding-edge processors, with all features included. * Fix a few DEBUG_TYPE to match other backends. Test Plan: ninja check Reviewers: sunfish Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D10880 llvm-svn: 241211
Diffstat (limited to 'llvm/lib/Target/WebAssembly/WebAssemblySubtarget.cpp')
-rw-r--r--llvm/lib/Target/WebAssembly/WebAssemblySubtarget.cpp6
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblySubtarget.cpp b/llvm/lib/Target/WebAssembly/WebAssemblySubtarget.cpp
index f1415ee..addea8e 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblySubtarget.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblySubtarget.cpp
@@ -19,7 +19,7 @@
#include "llvm/Support/TargetRegistry.h"
using namespace llvm;
-#define DEBUG_TYPE "subtarget"
+#define DEBUG_TYPE "wasm-subtarget"
#define GET_SUBTARGETINFO_CTOR
#define GET_SUBTARGETINFO_TARGET_DESC
@@ -40,8 +40,8 @@ WebAssemblySubtarget::WebAssemblySubtarget(const Triple &TT,
const std::string &CPU,
const std::string &FS,
const TargetMachine &TM)
- : WebAssemblyGenSubtargetInfo(TT, CPU, FS), HasSIMD(true), CPUString(CPU),
- TargetTriple(TT), FrameLowering(),
+ : WebAssemblyGenSubtargetInfo(TT, CPU, FS), HasSIMD128(false),
+ CPUString(CPU), TargetTriple(TT), FrameLowering(),
InstrInfo(initializeSubtargetDependencies(FS)),
TSInfo(TM.getDataLayout()), TLInfo(TM, *this) {}