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| author | Heejin Ahn <aheejin@gmail.com> | 2018-07-09 22:30:51 +0000 |
|---|---|---|
| committer | Heejin Ahn <aheejin@gmail.com> | 2018-07-09 22:30:51 +0000 |
| commit | fed7382ef695ae81769620dbeee74a058615e148 (patch) | |
| tree | 8c1b3bb8fa0d5434b65991f307f92ccca1b2aa32 /llvm/lib/Target/WebAssembly/WebAssemblySetP2AlignOperands.cpp | |
| parent | 703c872a4a64160cee299fae0144c9bf08949cc8 (diff) | |
| download | llvm-fed7382ef695ae81769620dbeee74a058615e148.zip llvm-fed7382ef695ae81769620dbeee74a058615e148.tar.gz llvm-fed7382ef695ae81769620dbeee74a058615e148.tar.bz2 | |
[WebAssembly] Support for binary atomic RMW instructions
Summary:
This adds support for binary atomic read-modify-write instructions:
add, sub, and, or, xor, and xchg.
This does not yet support translations of some of LLVM IR atomicrmw
instructions (nand, max, min, umax, and umin) that do not have a direct
counterpart in wasm instructions.
Reviewers: dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D49088
llvm-svn: 336615
Diffstat (limited to 'llvm/lib/Target/WebAssembly/WebAssemblySetP2AlignOperands.cpp')
| -rw-r--r-- | llvm/lib/Target/WebAssembly/WebAssemblySetP2AlignOperands.cpp | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblySetP2AlignOperands.cpp b/llvm/lib/Target/WebAssembly/WebAssemblySetP2AlignOperands.cpp index 6f0ae89..1422199 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblySetP2AlignOperands.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblySetP2AlignOperands.cpp @@ -107,6 +107,48 @@ bool WebAssemblySetP2AlignOperands::runOnMachineFunction(MachineFunction &MF) { case WebAssembly::ATOMIC_LOAD8_U_I64: case WebAssembly::ATOMIC_LOAD16_U_I64: case WebAssembly::ATOMIC_LOAD32_U_I64: + case WebAssembly::ATOMIC_RMW8_U_ADD_I32: + case WebAssembly::ATOMIC_RMW8_U_ADD_I64: + case WebAssembly::ATOMIC_RMW8_U_SUB_I32: + case WebAssembly::ATOMIC_RMW8_U_SUB_I64: + case WebAssembly::ATOMIC_RMW8_U_AND_I32: + case WebAssembly::ATOMIC_RMW8_U_AND_I64: + case WebAssembly::ATOMIC_RMW8_U_OR_I32: + case WebAssembly::ATOMIC_RMW8_U_OR_I64: + case WebAssembly::ATOMIC_RMW8_U_XOR_I32: + case WebAssembly::ATOMIC_RMW8_U_XOR_I64: + case WebAssembly::ATOMIC_RMW8_U_XCHG_I32: + case WebAssembly::ATOMIC_RMW8_U_XCHG_I64: + case WebAssembly::ATOMIC_RMW16_U_ADD_I32: + case WebAssembly::ATOMIC_RMW16_U_ADD_I64: + case WebAssembly::ATOMIC_RMW16_U_SUB_I32: + case WebAssembly::ATOMIC_RMW16_U_SUB_I64: + case WebAssembly::ATOMIC_RMW16_U_AND_I32: + case WebAssembly::ATOMIC_RMW16_U_AND_I64: + case WebAssembly::ATOMIC_RMW16_U_OR_I32: + case WebAssembly::ATOMIC_RMW16_U_OR_I64: + case WebAssembly::ATOMIC_RMW16_U_XOR_I32: + case WebAssembly::ATOMIC_RMW16_U_XOR_I64: + case WebAssembly::ATOMIC_RMW16_U_XCHG_I32: + case WebAssembly::ATOMIC_RMW16_U_XCHG_I64: + case WebAssembly::ATOMIC_RMW_ADD_I32: + case WebAssembly::ATOMIC_RMW32_U_ADD_I64: + case WebAssembly::ATOMIC_RMW_SUB_I32: + case WebAssembly::ATOMIC_RMW32_U_SUB_I64: + case WebAssembly::ATOMIC_RMW_AND_I32: + case WebAssembly::ATOMIC_RMW32_U_AND_I64: + case WebAssembly::ATOMIC_RMW_OR_I32: + case WebAssembly::ATOMIC_RMW32_U_OR_I64: + case WebAssembly::ATOMIC_RMW_XOR_I32: + case WebAssembly::ATOMIC_RMW32_U_XOR_I64: + case WebAssembly::ATOMIC_RMW_XCHG_I32: + case WebAssembly::ATOMIC_RMW32_U_XCHG_I64: + case WebAssembly::ATOMIC_RMW_ADD_I64: + case WebAssembly::ATOMIC_RMW_SUB_I64: + case WebAssembly::ATOMIC_RMW_AND_I64: + case WebAssembly::ATOMIC_RMW_OR_I64: + case WebAssembly::ATOMIC_RMW_XOR_I64: + case WebAssembly::ATOMIC_RMW_XCHG_I64: RewriteP2Align(MI, WebAssembly::LoadP2AlignOperandNo); break; case WebAssembly::STORE_I32: |