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| author | Sudharsan Veeravalli <quic_svs@quicinc.com> | 2025-06-16 12:28:12 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-06-16 12:28:12 +0530 |
| commit | 7d9a451d875368baece310ca7226e3adbc00e1bf (patch) | |
| tree | 2c27ffe35a0c3b539b9e0cf7e8ec5fd190ad78ef /llvm/lib/Target/WebAssembly/WebAssemblyRuntimeLibcallSignatures.cpp | |
| parent | f875efe1d82d920790e368f9ab2b31f173a523e1 (diff) | |
| download | llvm-7d9a451d875368baece310ca7226e3adbc00e1bf.zip llvm-7d9a451d875368baece310ca7226e3adbc00e1bf.tar.gz llvm-7d9a451d875368baece310ca7226e3adbc00e1bf.tar.bz2 | |
[RISCV] Change input register type for QC_SWM and QC_SWMI (#144294)
Version 0.13 of the `Xqci` spec changes the register type of input
operand `rs3` from `GPR` to `GPRNoX0` for these two instructions.
The spec can be found at
https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0
Diffstat (limited to 'llvm/lib/Target/WebAssembly/WebAssemblyRuntimeLibcallSignatures.cpp')
0 files changed, 0 insertions, 0 deletions