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author | Philip Reames <preames@rivosinc.com> | 2025-09-24 18:52:17 -0700 |
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committer | GitHub <noreply@github.com> | 2025-09-24 18:52:17 -0700 |
commit | ea721e2fa1cd2a35652082dae1d0987de531883d (patch) | |
tree | fa1f6f3bb4969140ffa7a727abefec9938070990 /llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp | |
parent | 151a80bbcea947a097870e8ce9034583936a357b (diff) | |
download | llvm-ea721e2fa1cd2a35652082dae1d0987de531883d.zip llvm-ea721e2fa1cd2a35652082dae1d0987de531883d.tar.gz llvm-ea721e2fa1cd2a35652082dae1d0987de531883d.tar.bz2 |
[TII] Split isTrivialReMaterializable into two versions [nfc] (#160377)
This change builds on https://github.com/llvm/llvm-project/pull/160319
which tries to clarify which *callers* (not backends) assume that the
result is actually trivial.
This change itself should be NFC. Essentially, I'm just renaming the
existing isTrivialRematerializable to the non-trivial version and then
adding a new trivial version (with the same name as the prior function)
and simplifying a few callers which want that semantic.
This change does *not* enable non-trivial remat any more broadly than
was already done for our targets which were lying through the old APIs;
that will come separately. The goal here is simply to make the code
easier to follow in terms of what assumptions are being made where.
---------
Co-authored-by: Luke Lau <luke_lau@icloud.com>
Diffstat (limited to 'llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp')
-rw-r--r-- | llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp index 7591541..08ca20b5 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp @@ -260,10 +260,7 @@ static void query(const MachineInstr &MI, bool &Read, bool &Write, // Test whether Def is safe and profitable to rematerialize. static bool shouldRematerialize(const MachineInstr &Def, const WebAssemblyInstrInfo *TII) { - return Def.isAsCheapAsAMove() && TII->isTriviallyReMaterializable(Def) && - llvm::all_of(Def.all_uses(), [](const MachineOperand &MO) { - return MO.getReg().isVirtual(); - }); + return Def.isAsCheapAsAMove() && TII->isTriviallyReMaterializable(Def); } // Identify the definition for this register at this point. This is a |